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sx128x.cpp 828623c70c21be0deedc7428e655c5ca37e7f814 (828623c7) Text, 25.25 KB
T8b949e// Copyright Sandeep Mistry, Mark Qvist and Jacob Eva.
T8b949e// Licensed under the MIT license.
Tff7b72#Tff7b72include T8b949e"Boards.h"
Tff7b72#Tff7b72if MODEM == SX1280
Tff7b72#Tff7b72include T8b949e"sx128x.h"
Tff7b72#Tff7b72define MCU_1284P 0x91
Tff7b72#Tff7b72define MCU_2560 0x92
Tff7b72#Tff7b72define MCU_ESP32 0x81
Tff7b72#Tff7b72define MCU_NRF52 0x71
Tff7b72#Tff7b72if defined(__AVR_ATmega1284P__)
Tff7b72#Tff7b72define PLATFORM PLATFORM_AVR
Tff7b72#Tff7b72define MCU_VARIANT MCU_1284P
Tff7b72#Tff7b72elif defined(__AVR_ATmega2560__)
Tff7b72#Tff7b72define PLATFORM PLATFORM_AVR
Tff7b72#Tff7b72define MCU_VARIANT MCU_2560
Tff7b72#Tff7b72elif defined(ESP32)
Tff7b72#Tff7b72define PLATFORM PLATFORM_ESP32
Tff7b72#Tff7b72define MCU_VARIANT MCU_ESP32
Tff7b72#Tff7b72elif defined(NRF52840_XXAA)
Tff7b72#Tff7b72define PLATFORM PLATFORM_NRF52
Tff7b72#Tff7b72define MCU_VARIANT MCU_NRF52
Tff7b72#Tff7b72endif
Tff7b72#Tff7b72ifndef MCU_VARIANT
Tff7b72#Tff7b72error No MCU variant defined, cannot compile
Tff7b72#Tff7b72endif
Tff7b72#Tff7b72if MCU_VARIANT == MCU_ESP32
Tff7b72#Tff7b72if MCU_VARIANT == MCU_ESP32 and !defined(CONFIG_IDF_TARGET_ESP32S3)
Tff7b72#Tff7b72include T8b949e"hal/wdt_hal.h"
Tff7b72#Tff7b72endif
Tff7b72#Tff7b72define ISR_VECT IRAM_ATTR
Tff7b72#Tff7b72else
Tff7b72#Tff7b72define ISR_VECT
Tff7b72#Tff7b72endif
T8b949e// SX128x registers
Tff7b72#Tff7b72define OP_RF_FREQ_8X 0x86
Tff7b72#Tff7b72define OP_SLEEP_8X 0x84
Tff7b72#Tff7b72define OP_STANDBY_8X 0x80
Tff7b72#Tff7b72define OP_TX_8X 0x83
Tff7b72#Tff7b72define OP_RX_8X 0x82
Tff7b72#Tff7b72define OP_SET_IRQ_FLAGS_8X 0x8D
Tff7b72#Tff7b72define OP_CLEAR_IRQ_STATUS_8X 0x97
Tff7b72#Tff7b72define OP_GET_IRQ_STATUS_8X 0x15
Tff7b72#Tff7b72define OP_RX_BUFFER_STATUS_8X 0x17
Tff7b72#Tff7b72define OP_PACKET_STATUS_8X 0x1D
Tff7b72#Tff7b72define OP_CURRENT_RSSI_8X 0x1F
Tff7b72#Tff7b72define OP_MODULATION_PARAMS_8X 0x8B
Tff7b72#Tff7b72define OP_PACKET_PARAMS_8X 0x8C
Tff7b72#Tff7b72define OP_STATUS_8X 0xC0
Tff7b72#Tff7b72define OP_TX_PARAMS_8X 0x8E
Tff7b72#Tff7b72define OP_PACKET_TYPE_8X 0x8A
Tff7b72#Tff7b72define OP_BUFFER_BASE_ADDR_8X 0x8F
Tff7b72#Tff7b72define OP_READ_REGISTER_8X 0x19
Tff7b72#Tff7b72define OP_WRITE_REGISTER_8X 0x18
Tff7b72#Tff7b72define IRQ_TX_DONE_MASK_8X 0x01
Tff7b72#Tff7b72define IRQ_RX_DONE_MASK_8X 0x02
Tff7b72#Tff7b72define IRQ_HEADER_DET_MASK_8X 0x10
Tff7b72#Tff7b72define IRQ_HEADER_ERROR_MASK_8X 0x20
Tff7b72#Tff7b72define IRQ_PAYLOAD_CRC_ERROR_MASK_8X 0x40
Tff7b72#Tff7b72define MODE_LONG_RANGE_MODE_8X 0x01
Tff7b72#Tff7b72define OP_FIFO_WRITE_8X 0x1A
Tff7b72#Tff7b72define OP_FIFO_READ_8X 0x1B
Tff7b72#Tff7b72define IRQ_PREAMBLE_DET_MASK_8X 0x80
Tff7b72#Tff7b72define REG_PACKET_SIZE 0x901
Tff7b72#Tff7b72define REG_FIRM_VER_MSB 0x154
Tff7b72#Tff7b72define REG_FIRM_VER_LSB 0x153
Tff7b72#Tff7b72define XTAL_FREQ_8X (double)52000000
Tff7b72#Tff7b72define FREQ_DIV_8X (double)pow(2.0, 18.0)
Tff7b72#Tff7b72define FREQ_STEP_8X (double)(XTAL_FREQ_8X Tff7b72/Tff7b72 FREQ_DIV_8X)
Tff7b72#Tff7b72if defined(NRF52840_XXAA)
Tff7b72extern Te6edf3SPIClass Te6edf3spiModemTb4b4b4;
Tff7b72#Tff7b72define SPI spiModem
Tff7b72#Tff7b72endif
Tff7b72extern Te6edf3SPIClass Te6edf3SPITb4b4b4;
Tff7b72#Tff7b72define MAX_PKT_LENGTH 255
Te6edf3sx128xTff7b72:Tff7b72:Te6edf3sx128xTb4b4b4(Tb4b4b4) Tff7b72:
Te6edf3_spiSettingsTb4b4b4(T79c0ff8E6Tb4b4b4, Te6edf3MSBFIRSTTb4b4b4, Te6edf3SPI_MODE0Tb4b4b4)Tb4b4b4,
Te6edf3_ssTb4b4b4(Te6edf3LORA_DEFAULT_SS_PINTb4b4b4)Tb4b4b4, Te6edf3_resetTb4b4b4(Te6edf3LORA_DEFAULT_RESET_PINTb4b4b4)Tb4b4b4, Te6edf3_dio0Tb4b4b4(Te6edf3LORA_DEFAULT_DIO0_PINTb4b4b4)Tb4b4b4, Te6edf3_rxenTb4b4b4(Te6edf3pin_rxenTb4b4b4)Tb4b4b4, Te6edf3_busyTb4b4b4(Te6edf3LORA_DEFAULT_BUSY_PINTb4b4b4)Tb4b4b4, Te6edf3_txenTb4b4b4(Te6edf3pin_txenTb4b4b4)Tb4b4b4,
Te6edf3_frequencyTb4b4b4(T79c0ff0Tb4b4b4)Tb4b4b4, Te6edf3_txpTb4b4b4(T79c0ff0Tb4b4b4)Tb4b4b4, Te6edf3_sfTb4b4b4(T79c0ff0x05Tb4b4b4)Tb4b4b4, Te6edf3_bwTb4b4b4(T79c0ff0x34Tb4b4b4)Tb4b4b4, Te6edf3_crTb4b4b4(T79c0ff0x01Tb4b4b4)Tb4b4b4, Te6edf3_packetIndexTb4b4b4(T79c0ff0Tb4b4b4)Tb4b4b4, Te6edf3_implicitHeaderModeTb4b4b4(T79c0ff0Tb4b4b4)Tb4b4b4, Te6edf3_payloadLengthTb4b4b4(T79c0ff255Tb4b4b4)Tb4b4b4, Te6edf3_crcModeTb4b4b4(T79c0ff0Tb4b4b4)Tb4b4b4, Te6edf3_fifo_tx_addr_ptrTb4b4b4(T79c0ff0Tb4b4b4)Tb4b4b4,
Te6edf3_fifo_rx_addr_ptrTb4b4b4(T79c0ff0Tb4b4b4)Tb4b4b4, Te6edf3_rxPacketLengthTb4b4b4(T79c0ff0Tb4b4b4)Tb4b4b4, Te6edf3_preinit_doneTb4b4b4(Tffa657falseTb4b4b4)Tb4b4b4, Te6edf3_tcxoTb4b4b4(Tffa657falseTb4b4b4) Tb4b4b4{ Te6edf3setTimeoutTb4b4b4(T79c0ff0Tb4b4b4)Tb4b4b4; Tb4b4b4}
Tffa657bool Te6edf3ISR_VECT Te6edf3sx128xTff7b72:Tff7b72:Te6edf3getPacketValidityTb4b4b4(Tb4b4b4) Tb4b4b4{
Tffa657uint8_t Te6edf3bufTb4b4b4[T79c0ff2Tb4b4b4]Tb4b4b4;
Te6edf3bufTb4b4b4[T79c0ff0Tb4b4b4] Tff7b72= T79c0ff0x00Tb4b4b4;
Te6edf3bufTb4b4b4[T79c0ff1Tb4b4b4] Tff7b72= T79c0ff0x00Tb4b4b4;
Te6edf3executeOpcodeReadTb4b4b4(Te6edf3OP_GET_IRQ_STATUS_8XTb4b4b4, Te6edf3bufTb4b4b4, T79c0ff2Tb4b4b4)Tb4b4b4;
Te6edf3executeOpcodeTb4b4b4(Te6edf3OP_CLEAR_IRQ_STATUS_8XTb4b4b4, Te6edf3bufTb4b4b4, T79c0ff2Tb4b4b4)Tb4b4b4;
Tff7b72if Tb4b4b4(Tb4b4b4(Te6edf3bufTb4b4b4[T79c0ff1Tb4b4b4] Tff7b72& Te6edf3IRQ_PAYLOAD_CRC_ERROR_MASK_8XTb4b4b4) Tff7b72=Tff7b72= T79c0ff0Tb4b4b4) Tb4b4b4{ Tff7b72return Tffa657trueTb4b4b4; Tb4b4b4}
Tff7b72else Tb4b4b4{ Tff7b72return Tffa657falseTb4b4b4; Tb4b4b4}
Tb4b4b4}
Tffa657void Te6edf3ISR_VECT Te6edf3sx128xTff7b72:Tff7b72:Te6edf3onDio0RiseTb4b4b4(Tb4b4b4) Tb4b4b4{
Te6edf3BaseType_t Te6edf3int_status Tff7b72= Te6edf3taskENTER_CRITICAL_FROM_ISRTb4b4b4(Tb4b4b4)Tb4b4b4;
T8b949e// On the SX1280, there is a bug which can cause the busy line
T8b949e// to remain high if a high amount of packets are received when
T8b949e// in continuous RX mode. This is documented as Errata 16.1 in
T8b949e// the SX1280 datasheet v3.2 (page 149)
T8b949e// Therefore, the modem is set into receive mode each time a packet is received.
Tff7b72if Tb4b4b4(Te6edf3sx128x_modemTb4b4b4.Te6edf3getPacketValidityTb4b4b4(Tb4b4b4)Tb4b4b4) Tb4b4b4{ Te6edf3sx128x_modemTb4b4b4.Te6edf3receiveTb4b4b4(Tb4b4b4)Tb4b4b4; Te6edf3sx128x_modemTb4b4b4.Te6edf3handleDio0RiseTb4b4b4(Tb4b4b4)Tb4b4b4; Tb4b4b4}
Tff7b72else Tb4b4b4{ Te6edf3sx128x_modemTb4b4b4.Te6edf3receiveTb4b4b4(Tb4b4b4)Tb4b4b4; Tb4b4b4}
Te6edf3taskEXIT_CRITICAL_FROM_ISRTb4b4b4(Te6edf3int_statusTb4b4b4)Tb4b4b4;
Tb4b4b4}
Tffa657void Te6edf3sx128xTff7b72:Tff7b72:Te6edf3handleDio0RiseTb4b4b4(Tb4b4b4) Tb4b4b4{
Te6edf3_packetIndex Tff7b72= T79c0ff0Tb4b4b4;
Tffa657uint8_t Te6edf3rxbufTb4b4b4[T79c0ff2Tb4b4b4] Tff7b72= Tb4b4b4{T79c0ff0Tb4b4b4}Tb4b4b4;
Te6edf3executeOpcodeReadTb4b4b4(Te6edf3OP_RX_BUFFER_STATUS_8XTb4b4b4, Te6edf3rxbufTb4b4b4, T79c0ff2Tb4b4b4)Tb4b4b4;
T8b949e// If implicit header mode is enabled, use pre-set packet length as payload length instead.
T8b949e// See SX1280 datasheet v3.2, page 92
Tff7b72if Tb4b4b4(Te6edf3_implicitHeaderMode Tff7b72=Tff7b72= T79c0ff0x80Tb4b4b4) Tb4b4b4{ Te6edf3_rxPacketLength Tff7b72= Te6edf3_payloadLengthTb4b4b4; Tb4b4b4}
Tff7b72else Tb4b4b4{ Te6edf3_rxPacketLength Tff7b72= Te6edf3rxbufTb4b4b4[T79c0ff0Tb4b4b4]Tb4b4b4; Tb4b4b4}
Tff7b72if Tb4b4b4(Te6edf3_receive_callbackTb4b4b4) Tb4b4b4{ Te6edf3_receive_callbackTb4b4b4(Te6edf3_rxPacketLengthTb4b4b4)Tb4b4b4; Tb4b4b4}
Tb4b4b4}
Tffa657bool Te6edf3sx128xTff7b72:Tff7b72:Te6edf3preInitTb4b4b4(Tb4b4b4) Tb4b4b4{
Te6edf3pinModeTb4b4b4(Te6edf3_ssTb4b4b4, Te6edf3OUTPUTTb4b4b4)Tb4b4b4;
Te6edf3digitalWriteTb4b4b4(Te6edf3_ssTb4b4b4, Te6edf3HIGHTb4b4b4)Tb4b4b4;
T8b949e// TODO: Check if this change causes issues on any platforms
Tff7b72#Tff7b72if MCU_VARIANT == MCU_ESP32
Tff7b72#Tff7b72if BOARD_MODEL == BOARD_T3S3 || BOARD_MODEL == BOARD_HELTEC32_V3 || BOARD_MODEL == BOARD_TDECK
Te6edf3SPITb4b4b4.Te6edf3beginTb4b4b4(Te6edf3pin_sclkTb4b4b4, Te6edf3pin_misoTb4b4b4, Te6edf3pin_mosiTb4b4b4, Te6edf3pin_csTb4b4b4)Tb4b4b4;
Tff7b72#Tff7b72else
Te6edf3SPITb4b4b4.Te6edf3beginTb4b4b4(Tb4b4b4)Tb4b4b4;
Tff7b72#Tff7b72endif
Tff7b72#Tff7b72else
Te6edf3SPITb4b4b4.Te6edf3beginTb4b4b4(Tb4b4b4)Tb4b4b4;
Tff7b72#Tff7b72endif
T8b949e// Detect modem (retry for up to 500ms)
Tffa657long Te6edf3start Tff7b72= Te6edf3millisTb4b4b4(Tb4b4b4)Tb4b4b4;
Tffa657uint8_t Te6edf3version_msbTb4b4b4;
Tffa657uint8_t Te6edf3version_lsbTb4b4b4;
Tff7b72while Tb4b4b4(Tb4b4b4(Tb4b4b4(Te6edf3millisTb4b4b4(Tb4b4b4) Tff7b72- Te6edf3startTb4b4b4) Tff7b72< T79c0ff500Tb4b4b4) Tff7b72&Tff7b72& Tb4b4b4(Te6edf3millisTb4b4b4(Tb4b4b4) Tff7b72>Tff7b72= Te6edf3startTb4b4b4)Tb4b4b4) Tb4b4b4{
Te6edf3version_msb Tff7b72= Te6edf3readRegisterTb4b4b4(Te6edf3REG_FIRM_VER_MSBTb4b4b4)Tb4b4b4;
Te6edf3version_lsb Tff7b72= Te6edf3readRegisterTb4b4b4(Te6edf3REG_FIRM_VER_LSBTb4b4b4)Tb4b4b4;
Tff7b72if Tb4b4b4(Tb4b4b4(Te6edf3version_msb Tff7b72=Tff7b72= T79c0ff0xB7 Tff7b72&Tff7b72& Te6edf3version_lsb Tff7b72=Tff7b72= T79c0ff0xA9Tb4b4b4) Tff7b72|Tff7b72| Tb4b4b4(Te6edf3version_msb Tff7b72=Tff7b72= T79c0ff0xB5 Tff7b72&Tff7b72& Te6edf3version_lsb Tff7b72=Tff7b72= T79c0ff0xA9Tb4b4b4)Tb4b4b4) Tb4b4b4{ Tff7b72breakTb4b4b4; Tb4b4b4}
Te6edf3delayTb4b4b4(T79c0ff100Tb4b4b4)Tb4b4b4;
Tb4b4b4}
Tff7b72if Tb4b4b4(Tb4b4b4(Te6edf3version_msb Tff7b72!Tff7b72= T79c0ff0xB7 Tff7b72|Tff7b72| Te6edf3version_lsb Tff7b72!Tff7b72= T79c0ff0xA9Tb4b4b4) Tff7b72&Tff7b72& Tb4b4b4(Te6edf3version_msb Tff7b72!Tff7b72= T79c0ff0xB5 Tff7b72|Tff7b72| Te6edf3version_lsb Tff7b72!Tff7b72= T79c0ff0xA9Tb4b4b4)Tb4b4b4) Tb4b4b4{ Tff7b72return Tffa657falseTb4b4b4; Tb4b4b4}
Te6edf3_preinit_done Tff7b72= Tffa657trueTb4b4b4;
Tff7b72return Tffa657trueTb4b4b4;
Tb4b4b4}
Tffa657uint8_t Te6edf3ISR_VECT Te6edf3sx128xTff7b72:Tff7b72:Te6edf3readRegisterTb4b4b4(Tffa657uint16_t Te6edf3addressTb4b4b4) Tb4b4b4{ Tff7b72return Te6edf3singleTransferTb4b4b4(Te6edf3OP_READ_REGISTER_8XTb4b4b4, Te6edf3addressTb4b4b4, T79c0ff0x00Tb4b4b4)Tb4b4b4; Tb4b4b4}
Tffa657void Te6edf3sx128xTff7b72:Tff7b72:Te6edf3writeRegisterTb4b4b4(Tffa657uint16_t Te6edf3addressTb4b4b4, Tffa657uint8_t Te6edf3valueTb4b4b4) Tb4b4b4{ Te6edf3singleTransferTb4b4b4(Te6edf3OP_WRITE_REGISTER_8XTb4b4b4, Te6edf3addressTb4b4b4, Te6edf3valueTb4b4b4)Tb4b4b4; Tb4b4b4}
Tffa657uint8_t Te6edf3ISR_VECT Te6edf3sx128xTff7b72:Tff7b72:Te6edf3singleTransferTb4b4b4(Tffa657uint8_t Te6edf3opcodeTb4b4b4, Tffa657uint16_t Te6edf3addressTb4b4b4, Tffa657uint8_t Te6edf3valueTb4b4b4) Tb4b4b4{
Te6edf3waitOnBusyTb4b4b4(Tb4b4b4)Tb4b4b4;
Tffa657uint8_t Te6edf3responseTb4b4b4;
Te6edf3digitalWriteTb4b4b4(Te6edf3_ssTb4b4b4, Te6edf3LOWTb4b4b4)Tb4b4b4;
Te6edf3SPITb4b4b4.Te6edf3beginTransactionTb4b4b4(Te6edf3_spiSettingsTb4b4b4)Tb4b4b4;
Te6edf3SPITb4b4b4.Te6edf3transferTb4b4b4(Te6edf3opcodeTb4b4b4)Tb4b4b4;
Te6edf3SPITb4b4b4.Te6edf3transferTb4b4b4(Tb4b4b4(Te6edf3address Tff7b72& T79c0ff0xFF00Tb4b4b4) Tff7b72>Tff7b72> T79c0ff8Tb4b4b4)Tb4b4b4;
Te6edf3SPITb4b4b4.Te6edf3transferTb4b4b4(Te6edf3address Tff7b72& T79c0ff0x00FFTb4b4b4)Tb4b4b4;
Tff7b72if Tb4b4b4(Te6edf3opcode Tff7b72=Tff7b72= Te6edf3OP_READ_REGISTER_8XTb4b4b4) Tb4b4b4{ Te6edf3SPITb4b4b4.Te6edf3transferTb4b4b4(T79c0ff0x00Tb4b4b4)Tb4b4b4; Tb4b4b4}
Te6edf3response Tff7b72= Te6edf3SPITb4b4b4.Te6edf3transferTb4b4b4(Te6edf3valueTb4b4b4)Tb4b4b4;
Te6edf3SPITb4b4b4.Te6edf3endTransactionTb4b4b4(Tb4b4b4)Tb4b4b4;
Te6edf3digitalWriteTb4b4b4(Te6edf3_ssTb4b4b4, Te6edf3HIGHTb4b4b4)Tb4b4b4;
Tff7b72return Te6edf3responseTb4b4b4;
Tb4b4b4}
Tffa657void Te6edf3sx128xTff7b72:Tff7b72:Te6edf3rxAntEnableTb4b4b4(Tb4b4b4) Tb4b4b4{
Tff7b72if Tb4b4b4(Te6edf3_txen Tff7b72!Tff7b72= T79c0ff-1Tb4b4b4) Tb4b4b4{ Te6edf3digitalWriteTb4b4b4(Te6edf3_txenTb4b4b4, Te6edf3LOWTb4b4b4)Tb4b4b4; Tb4b4b4}
Tff7b72if Tb4b4b4(Te6edf3_rxen Tff7b72!Tff7b72= T79c0ff-1Tb4b4b4) Tb4b4b4{ Te6edf3digitalWriteTb4b4b4(Te6edf3_rxenTb4b4b4, Te6edf3HIGHTb4b4b4)Tb4b4b4; Tb4b4b4}
Tb4b4b4}
Tffa657void Te6edf3sx128xTff7b72:Tff7b72:Te6edf3txAntEnableTb4b4b4(Tb4b4b4) Tb4b4b4{
Tff7b72if Tb4b4b4(Te6edf3_txen Tff7b72!Tff7b72= T79c0ff-1Tb4b4b4) Tb4b4b4{ Te6edf3digitalWriteTb4b4b4(Te6edf3_txenTb4b4b4, Te6edf3HIGHTb4b4b4)Tb4b4b4; Tb4b4b4}
Tff7b72if Tb4b4b4(Te6edf3_rxen Tff7b72!Tff7b72= T79c0ff-1Tb4b4b4) Tb4b4b4{ Te6edf3digitalWriteTb4b4b4(Te6edf3_rxenTb4b4b4, Te6edf3LOWTb4b4b4)Tb4b4b4; Tb4b4b4}
Tb4b4b4}
Tffa657void Te6edf3sx128xTff7b72:Tff7b72:Te6edf3loraModeTb4b4b4(Tb4b4b4) Tb4b4b4{
Tffa657uint8_t Te6edf3mode Tff7b72= Te6edf3MODE_LONG_RANGE_MODE_8XTb4b4b4;
Te6edf3executeOpcodeTb4b4b4(Te6edf3OP_PACKET_TYPE_8XTb4b4b4, Tff7b72&Te6edf3modeTb4b4b4, T79c0ff1Tb4b4b4)Tb4b4b4;
Tb4b4b4}
Tffa657void Te6edf3sx128xTff7b72:Tff7b72:Te6edf3waitOnBusyTb4b4b4(Tb4b4b4) Tb4b4b4{
Tffa657unsigned Tffa657long Te6edf3time Tff7b72= Te6edf3millisTb4b4b4(Tb4b4b4)Tb4b4b4;
Tff7b72while Tb4b4b4(Te6edf3digitalReadTb4b4b4(Te6edf3_busyTb4b4b4) Tff7b72=Tff7b72= Te6edf3HIGHTb4b4b4) Tb4b4b4{
Tff7b72if Tb4b4b4(Te6edf3millisTb4b4b4(Tb4b4b4) Tff7b72>Tff7b72= Tb4b4b4(Te6edf3time Tff7b72+ T79c0ff100Tb4b4b4)Tb4b4b4) Tb4b4b4{ Tff7b72breakTb4b4b4; Tb4b4b4}
Tb4b4b4}
Tb4b4b4}
Tffa657void Te6edf3sx128xTff7b72:Tff7b72:Te6edf3executeOpcodeTb4b4b4(Tffa657uint8_t Te6edf3opcodeTb4b4b4, Tffa657uint8_t Tff7b72*Te6edf3bufferTb4b4b4, Tffa657uint8_t Te6edf3sizeTb4b4b4) Tb4b4b4{
Te6edf3waitOnBusyTb4b4b4(Tb4b4b4)Tb4b4b4;
Te6edf3digitalWriteTb4b4b4(Te6edf3_ssTb4b4b4, Te6edf3LOWTb4b4b4)Tb4b4b4;
Te6edf3SPITb4b4b4.Te6edf3beginTransactionTb4b4b4(Te6edf3_spiSettingsTb4b4b4)Tb4b4b4;
Te6edf3SPITb4b4b4.Te6edf3transferTb4b4b4(Te6edf3opcodeTb4b4b4)Tb4b4b4;
Tff7b72for Tb4b4b4(Tffa657int Te6edf3i Tff7b72= T79c0ff0Tb4b4b4; Te6edf3i Tff7b72< Te6edf3sizeTb4b4b4; Te6edf3iTff7b72+Tff7b72+Tb4b4b4) Tb4b4b4{ Te6edf3SPITb4b4b4.Te6edf3transferTb4b4b4(Te6edf3bufferTb4b4b4[Te6edf3iTb4b4b4]Tb4b4b4)Tb4b4b4; Tb4b4b4}
Te6edf3SPITb4b4b4.Te6edf3endTransactionTb4b4b4(Tb4b4b4)Tb4b4b4;
Te6edf3digitalWriteTb4b4b4(Te6edf3_ssTb4b4b4, Te6edf3HIGHTb4b4b4)Tb4b4b4;
Tb4b4b4}
Tffa657void Te6edf3sx128xTff7b72:Tff7b72:Te6edf3executeOpcodeReadTb4b4b4(Tffa657uint8_t Te6edf3opcodeTb4b4b4, Tffa657uint8_t Tff7b72*Te6edf3bufferTb4b4b4, Tffa657uint8_t Te6edf3sizeTb4b4b4) Tb4b4b4{
Te6edf3waitOnBusyTb4b4b4(Tb4b4b4)Tb4b4b4;
Te6edf3digitalWriteTb4b4b4(Te6edf3_ssTb4b4b4, Te6edf3LOWTb4b4b4)Tb4b4b4;
Te6edf3SPITb4b4b4.Te6edf3beginTransactionTb4b4b4(Te6edf3_spiSettingsTb4b4b4)Tb4b4b4;
Te6edf3SPITb4b4b4.Te6edf3transferTb4b4b4(Te6edf3opcodeTb4b4b4)Tb4b4b4;
Te6edf3SPITb4b4b4.Te6edf3transferTb4b4b4(T79c0ff0x00Tb4b4b4)Tb4b4b4;
Tff7b72for Tb4b4b4(Tffa657int Te6edf3i Tff7b72= T79c0ff0Tb4b4b4; Te6edf3i Tff7b72< Te6edf3sizeTb4b4b4; Te6edf3iTff7b72+Tff7b72+Tb4b4b4) Tb4b4b4{ Te6edf3bufferTb4b4b4[Te6edf3iTb4b4b4] Tff7b72= Te6edf3SPITb4b4b4.Te6edf3transferTb4b4b4(T79c0ff0x00Tb4b4b4)Tb4b4b4; Tb4b4b4}
Te6edf3SPITb4b4b4.Te6edf3endTransactionTb4b4b4(Tb4b4b4)Tb4b4b4;
Te6edf3digitalWriteTb4b4b4(Te6edf3_ssTb4b4b4, Te6edf3HIGHTb4b4b4)Tb4b4b4;
Tb4b4b4}
Tffa657void Te6edf3sx128xTff7b72:Tff7b72:Te6edf3writeBufferTb4b4b4(Tff7b72const Tffa657uint8_tTff7b72* Te6edf3bufferTb4b4b4, Tffa657size_t Te6edf3sizeTb4b4b4) Tb4b4b4{
Te6edf3waitOnBusyTb4b4b4(Tb4b4b4)Tb4b4b4;
Te6edf3digitalWriteTb4b4b4(Te6edf3_ssTb4b4b4, Te6edf3LOWTb4b4b4)Tb4b4b4;
Te6edf3SPITb4b4b4.Te6edf3beginTransactionTb4b4b4(Te6edf3_spiSettingsTb4b4b4)Tb4b4b4;
Te6edf3SPITb4b4b4.Te6edf3transferTb4b4b4(Te6edf3OP_FIFO_WRITE_8XTb4b4b4)Tb4b4b4;
Te6edf3SPITb4b4b4.Te6edf3transferTb4b4b4(Te6edf3_fifo_tx_addr_ptrTb4b4b4)Tb4b4b4;
Tff7b72for Tb4b4b4(Tffa657int Te6edf3i Tff7b72= T79c0ff0Tb4b4b4; Te6edf3i Tff7b72< Te6edf3sizeTb4b4b4; Te6edf3iTff7b72+Tff7b72+Tb4b4b4) Tb4b4b4{ Te6edf3SPITb4b4b4.Te6edf3transferTb4b4b4(Te6edf3bufferTb4b4b4[Te6edf3iTb4b4b4]Tb4b4b4)Tb4b4b4; Te6edf3_fifo_tx_addr_ptrTff7b72+Tff7b72+Tb4b4b4; Tb4b4b4}
Te6edf3SPITb4b4b4.Te6edf3endTransactionTb4b4b4(Tb4b4b4)Tb4b4b4;
Te6edf3digitalWriteTb4b4b4(Te6edf3_ssTb4b4b4, Te6edf3HIGHTb4b4b4)Tb4b4b4;
Tb4b4b4}
Tffa657void Te6edf3sx128xTff7b72:Tff7b72:Te6edf3readBufferTb4b4b4(Tffa657uint8_tTff7b72* Te6edf3bufferTb4b4b4, Tffa657size_t Te6edf3sizeTb4b4b4) Tb4b4b4{
Te6edf3waitOnBusyTb4b4b4(Tb4b4b4)Tb4b4b4;
Te6edf3digitalWriteTb4b4b4(Te6edf3_ssTb4b4b4, Te6edf3LOWTb4b4b4)Tb4b4b4;
Te6edf3SPITb4b4b4.Te6edf3beginTransactionTb4b4b4(Te6edf3_spiSettingsTb4b4b4)Tb4b4b4;
Te6edf3SPITb4b4b4.Te6edf3transferTb4b4b4(Te6edf3OP_FIFO_READ_8XTb4b4b4)Tb4b4b4;
Te6edf3SPITb4b4b4.Te6edf3transferTb4b4b4(Te6edf3_fifo_rx_addr_ptrTb4b4b4)Tb4b4b4;
Te6edf3SPITb4b4b4.Te6edf3transferTb4b4b4(T79c0ff0x00Tb4b4b4)Tb4b4b4;
Tff7b72for Tb4b4b4(Tffa657int Te6edf3i Tff7b72= T79c0ff0Tb4b4b4; Te6edf3i Tff7b72< Te6edf3sizeTb4b4b4; Te6edf3iTff7b72+Tff7b72+Tb4b4b4) Tb4b4b4{ Te6edf3bufferTb4b4b4[Te6edf3iTb4b4b4] Tff7b72= Te6edf3SPITb4b4b4.Te6edf3transferTb4b4b4(T79c0ff0x00Tb4b4b4)Tb4b4b4; Tb4b4b4}
Te6edf3SPITb4b4b4.Te6edf3endTransactionTb4b4b4(Tb4b4b4)Tb4b4b4;
Te6edf3digitalWriteTb4b4b4(Te6edf3_ssTb4b4b4, Te6edf3HIGHTb4b4b4)Tb4b4b4;
Tb4b4b4}
Tffa657void Te6edf3sx128xTff7b72:Tff7b72:Te6edf3setModulationParamsTb4b4b4(Tffa657uint8_t Te6edf3sfTb4b4b4, Tffa657uint8_t Te6edf3bwTb4b4b4, Tffa657uint8_t Te6edf3crTb4b4b4) Tb4b4b4{
T8b949e// because there is no access to these registers on the sx1280, we have
T8b949e// to set all these parameters at once or not at all.
Tffa657uint8_t Te6edf3bufTb4b4b4[T79c0ff3Tb4b4b4]Tb4b4b4;
Te6edf3bufTb4b4b4[T79c0ff0Tb4b4b4] Tff7b72= Te6edf3sf Tff7b72<Tff7b72< T79c0ff4Tb4b4b4;
Te6edf3bufTb4b4b4[T79c0ff1Tb4b4b4] Tff7b72= Te6edf3bwTb4b4b4;
Te6edf3bufTb4b4b4[T79c0ff2Tb4b4b4] Tff7b72= Te6edf3crTb4b4b4;
Te6edf3executeOpcodeTb4b4b4(Te6edf3OP_MODULATION_PARAMS_8XTb4b4b4, Te6edf3bufTb4b4b4, T79c0ff3Tb4b4b4)Tb4b4b4;
Tff7b72if Tb4b4b4(Te6edf3sf Tff7b72<Tff7b72= T79c0ff6Tb4b4b4) Tb4b4b4{ Te6edf3writeRegisterTb4b4b4(T79c0ff0x925Tb4b4b4, T79c0ff0x1ETb4b4b4)Tb4b4b4; Tb4b4b4}
Tff7b72else Tff7b72if Tb4b4b4(Te6edf3sf Tff7b72<Tff7b72= T79c0ff8Tb4b4b4) Tb4b4b4{ Te6edf3writeRegisterTb4b4b4(T79c0ff0x925Tb4b4b4, T79c0ff0x37Tb4b4b4)Tb4b4b4; Tb4b4b4}
Tff7b72else Tff7b72if Tb4b4b4(Te6edf3sf Tff7b72>Tff7b72= T79c0ff9Tb4b4b4) Tb4b4b4{ Te6edf3writeRegisterTb4b4b4(T79c0ff0x925Tb4b4b4, T79c0ff0x32Tb4b4b4)Tb4b4b4; Tb4b4b4}
Te6edf3writeRegisterTb4b4b4(T79c0ff0x093CTb4b4b4, T79c0ff0x1Tb4b4b4)Tb4b4b4;
Tb4b4b4}
Tffa657uint8_t Te6edf3preamble_e Tff7b72= T79c0ff0Tb4b4b4;
Tffa657uint8_t Te6edf3preamble_m Tff7b72= T79c0ff0Tb4b4b4;
Tffa657uint32_t Te6edf3last_me_result_target Tff7b72= T79c0ff0Tb4b4b4;
Tff7b72extern Tffa657long Te6edf3lora_preamble_symbolsTb4b4b4;
Tffa657void Td2a8ffsx128x::setPacketParamsTb4b4b4(Tffa657uint32_t Te6edf3target_preamble_symbolsTb4b4b4, Tffa657uint8_t Te6edf3headermodeTb4b4b4, Tffa657uint8_t Te6edf3payload_lengthTb4b4b4, Tffa657uint8_t Te6edf3crcTb4b4b4) Tb4b4b4{
Tff7b72if Tb4b4b4(Te6edf3last_me_result_target Tff7b72!Tff7b72= Te6edf3target_preamble_symbolsTb4b4b4) Tb4b4b4{
T8b949e// Calculate exponent and mantissa values for modem
Tff7b72if Tb4b4b4(Te6edf3target_preamble_symbols Tff7b72>Tff7b72= T79c0ff0xF000Tb4b4b4) Te6edf3target_preamble_symbols Tff7b72= T79c0ff0xF000Tb4b4b4;
Tffa657uint32_t Te6edf3calculated_preamble_symbolsTb4b4b4;
Tffa657uint8_t Te6edf3e Tff7b72= T79c0ff1Tb4b4b4;
Tffa657uint8_t Te6edf3m Tff7b72= T79c0ff1Tb4b4b4;
Tff7b72while Tb4b4b4(Te6edf3e Tff7b72<Tff7b72= T79c0ff15Tb4b4b4) Tb4b4b4{
Tff7b72while Tb4b4b4(Te6edf3m Tff7b72<Tff7b72= T79c0ff15Tb4b4b4) Tb4b4b4{
Te6edf3calculated_preamble_symbols Tff7b72= Te6edf3m Tff7b72* Tb4b4b4(Te6edf3powTb4b4b4(T79c0ff2Tb4b4b4,Te6edf3eTb4b4b4)Tb4b4b4)Tb4b4b4;
Tff7b72if Tb4b4b4(Te6edf3calculated_preamble_symbols Tff7b72>Tff7b72= Te6edf3target_preamble_symbolsT79c0ff-4Tb4b4b4) Tff7b72breakTb4b4b4;
Te6edf3mTff7b72+Tff7b72+Tb4b4b4;
Tb4b4b4}
Tff7b72if Tb4b4b4(Te6edf3calculated_preamble_symbols Tff7b72>Tff7b72= Te6edf3target_preamble_symbolsT79c0ff-4Tb4b4b4) Tff7b72breakTb4b4b4;
Te6edf3m Tff7b72= T79c0ff1Tb4b4b4; Te6edf3eTff7b72+Tff7b72+Tb4b4b4;
Tb4b4b4}
Te6edf3last_me_result_target Tff7b72= Te6edf3target_preamble_symbolsTb4b4b4;
Te6edf3lora_preamble_symbols Tff7b72= Te6edf3calculated_preamble_symbolsTff7b72+T79c0ff4Tb4b4b4;
Te6edf3_preambleLength Tff7b72= Te6edf3lora_preamble_symbolsTb4b4b4;
Te6edf3preamble_e Tff7b72= Te6edf3eTb4b4b4;
Te6edf3preamble_m Tff7b72= Te6edf3mTb4b4b4;
Tb4b4b4}
Tffa657uint8_t Te6edf3bufTb4b4b4[T79c0ff7Tb4b4b4]Tb4b4b4;
Te6edf3bufTb4b4b4[T79c0ff0Tb4b4b4] Tff7b72= Tb4b4b4(Te6edf3preamble_e Tff7b72<Tff7b72< T79c0ff4Tb4b4b4) Tff7b72| Te6edf3preamble_mTb4b4b4;
Te6edf3bufTb4b4b4[T79c0ff1Tb4b4b4] Tff7b72= Te6edf3headermodeTb4b4b4;
Te6edf3bufTb4b4b4[T79c0ff2Tb4b4b4] Tff7b72= Te6edf3payload_lengthTb4b4b4;
Te6edf3bufTb4b4b4[T79c0ff3Tb4b4b4] Tff7b72= Te6edf3crcTb4b4b4;
Te6edf3bufTb4b4b4[T79c0ff4Tb4b4b4] Tff7b72= T79c0ff0x40Tb4b4b4; T8b949e// Standard IQ setting (no inversion)
Te6edf3bufTb4b4b4[T79c0ff5Tb4b4b4] Tff7b72= T79c0ff0x00Tb4b4b4; T8b949e// Unused params
Te6edf3bufTb4b4b4[T79c0ff6Tb4b4b4] Tff7b72= T79c0ff0x00Tb4b4b4;
Te6edf3executeOpcodeTb4b4b4(Te6edf3OP_PACKET_PARAMS_8XTb4b4b4, Te6edf3bufTb4b4b4, T79c0ff7Tb4b4b4)Tb4b4b4;
Tb4b4b4}
Tffa657void Td2a8ffsx128x::resetTb4b4b4(Tb4b4b4) Tb4b4b4{
Tff7b72if Tb4b4b4(Te6edf3_reset Tff7b72!Tff7b72= T79c0ff-1Tb4b4b4) Tb4b4b4{
Te6edf3pinModeTb4b4b4(Te6edf3_resetTb4b4b4, Te6edf3OUTPUTTb4b4b4)Tb4b4b4;
Te6edf3digitalWriteTb4b4b4(Te6edf3_resetTb4b4b4, Te6edf3LOWTb4b4b4)Tb4b4b4;
Te6edf3delayTb4b4b4(T79c0ff10Tb4b4b4)Tb4b4b4;
Te6edf3digitalWriteTb4b4b4(Te6edf3_resetTb4b4b4, Te6edf3HIGHTb4b4b4)Tb4b4b4;
Te6edf3delayTb4b4b4(T79c0ff10Tb4b4b4)Tb4b4b4;
Tb4b4b4}
Tb4b4b4}
Tffa657int Td2a8ffsx128x::beginTb4b4b4(Tffa657unsigned Tffa657long Te6edf3frequencyTb4b4b4) Tb4b4b4{
Te6edf3resetTb4b4b4(Tb4b4b4)Tb4b4b4;
Tff7b72if Tb4b4b4(Te6edf3_rxen Tff7b72!Tff7b72= T79c0ff-1Tb4b4b4) Tb4b4b4{ Te6edf3pinModeTb4b4b4(Te6edf3_rxenTb4b4b4, Te6edf3OUTPUTTb4b4b4)Tb4b4b4; Tb4b4b4}
Tff7b72if Tb4b4b4(Te6edf3_txen Tff7b72!Tff7b72= T79c0ff-1Tb4b4b4) Tb4b4b4{ Te6edf3pinModeTb4b4b4(Te6edf3_txenTb4b4b4, Te6edf3OUTPUTTb4b4b4)Tb4b4b4; Tb4b4b4}
Tff7b72if Tb4b4b4(Te6edf3_busy Tff7b72!Tff7b72= T79c0ff-1Tb4b4b4) Tb4b4b4{ Te6edf3pinModeTb4b4b4(Te6edf3_busyTb4b4b4, Te6edf3INPUTTb4b4b4)Tb4b4b4; Tb4b4b4}
Tff7b72if Tb4b4b4(Tff7b72!Te6edf3_preinit_doneTb4b4b4) Tb4b4b4{
Tff7b72if Tb4b4b4(Tff7b72!Te6edf3preInitTb4b4b4(Tb4b4b4)Tb4b4b4) Tb4b4b4{
Tff7b72return Tffa657falseTb4b4b4;
Tb4b4b4}
Tb4b4b4}
Te6edf3standbyTb4b4b4(Tb4b4b4)Tb4b4b4;
Te6edf3loraModeTb4b4b4(Tb4b4b4)Tb4b4b4;
Te6edf3rxAntEnableTb4b4b4(Tb4b4b4)Tb4b4b4;
Te6edf3setFrequencyTb4b4b4(Te6edf3frequencyTb4b4b4)Tb4b4b4;
T8b949e// TODO: Implement LNA boost
T8b949e//writeRegister(REG_LNA, 0x96);
Te6edf3setModulationParamsTb4b4b4(Te6edf3_sfTb4b4b4, Te6edf3_bwTb4b4b4, Te6edf3_crTb4b4b4)Tb4b4b4;
Te6edf3setPacketParamsTb4b4b4(Te6edf3_preambleLengthTb4b4b4, Te6edf3_implicitHeaderModeTb4b4b4, Te6edf3_payloadLengthTb4b4b4, Te6edf3_crcModeTb4b4b4)Tb4b4b4;
Te6edf3setTxPowerTb4b4b4(Te6edf3_txpTb4b4b4)Tb4b4b4;
T8b949e// Set base addresses
Tffa657uint8_t Te6edf3basebufTb4b4b4[T79c0ff2Tb4b4b4] Tff7b72= Tb4b4b4{T79c0ff0Tb4b4b4}Tb4b4b4;
Te6edf3executeOpcodeTb4b4b4(Te6edf3OP_BUFFER_BASE_ADDR_8XTb4b4b4, Te6edf3basebufTb4b4b4, T79c0ff2Tb4b4b4)Tb4b4b4;
Te6edf3_radio_online Tff7b72= Tffa657trueTb4b4b4;
Tff7b72return T79c0ff1Tb4b4b4;
Tb4b4b4}
Tffa657void Td2a8ffsx128x::endTb4b4b4(Tb4b4b4) Tb4b4b4{
Te6edf3sleepTb4b4b4(Tb4b4b4)Tb4b4b4;
Te6edf3SPITb4b4b4.Te6edf3endTb4b4b4(Tb4b4b4)Tb4b4b4;
Te6edf3_bitrate Tff7b72= T79c0ff0Tb4b4b4;
Te6edf3_radio_online Tff7b72= Tffa657falseTb4b4b4;
Te6edf3_preinit_done Tff7b72= Tffa657falseTb4b4b4;
Tb4b4b4}
Tffa657int Td2a8ffsx128x::beginPacketTb4b4b4(Tffa657int Te6edf3implicitHeaderTb4b4b4) Tb4b4b4{
Te6edf3standbyTb4b4b4(Tb4b4b4)Tb4b4b4;
Tff7b72if Tb4b4b4(Te6edf3implicitHeaderTb4b4b4) Tb4b4b4{ Te6edf3implicitHeaderModeTb4b4b4(Tb4b4b4)Tb4b4b4; Tb4b4b4}
Tff7b72else Tb4b4b4{ Te6edf3explicitHeaderModeTb4b4b4(Tb4b4b4)Tb4b4b4; Tb4b4b4}
Te6edf3_payloadLength Tff7b72= T79c0ff0Tb4b4b4;
Te6edf3_fifo_tx_addr_ptr Tff7b72= T79c0ff0Tb4b4b4;
Te6edf3setPacketParamsTb4b4b4(Te6edf3_preambleLengthTb4b4b4, Te6edf3_implicitHeaderModeTb4b4b4, Te6edf3_payloadLengthTb4b4b4, Te6edf3_crcModeTb4b4b4)Tb4b4b4;
Tff7b72return T79c0ff1Tb4b4b4;
Tb4b4b4}
Tffa657int Td2a8ffsx128x::endPacketTb4b4b4(Tb4b4b4) Tb4b4b4{
Te6edf3setPacketParamsTb4b4b4(Te6edf3_preambleLengthTb4b4b4, Te6edf3_implicitHeaderModeTb4b4b4, Te6edf3_payloadLengthTb4b4b4, Te6edf3_crcModeTb4b4b4)Tb4b4b4;
Te6edf3txAntEnableTb4b4b4(Tb4b4b4)Tb4b4b4;
T8b949e// Put in single TX mode
Tffa657uint8_t Te6edf3timeoutTb4b4b4[T79c0ff3Tb4b4b4] Tff7b72= Tb4b4b4{T79c0ff0Tb4b4b4}Tb4b4b4;
Te6edf3executeOpcodeTb4b4b4(Te6edf3OP_TX_8XTb4b4b4, Te6edf3timeoutTb4b4b4, T79c0ff3Tb4b4b4)Tb4b4b4;
Tffa657uint8_t Te6edf3bufTb4b4b4[T79c0ff2Tb4b4b4]Tb4b4b4;
Te6edf3bufTb4b4b4[T79c0ff0Tb4b4b4] Tff7b72= T79c0ff0x00Tb4b4b4;
Te6edf3bufTb4b4b4[T79c0ff1Tb4b4b4] Tff7b72= T79c0ff0x00Tb4b4b4;
Te6edf3executeOpcodeReadTb4b4b4(Te6edf3OP_GET_IRQ_STATUS_8XTb4b4b4, Te6edf3bufTb4b4b4, T79c0ff2Tb4b4b4)Tb4b4b4;
T8b949e// Wait for TX done
Tffa657bool Te6edf3timed_out Tff7b72= Tffa657falseTb4b4b4;
Tffa657uint32_t Te6edf3w_timeout Tff7b72= Te6edf3millisTb4b4b4(Tb4b4b4)Tff7b72+Te6edf3LORA_MODEM_TIMEOUT_MSTb4b4b4;
Tff7b72while Tb4b4b4(Tb4b4b4(Te6edf3millisTb4b4b4(Tb4b4b4) Tff7b72< Te6edf3w_timeoutTb4b4b4) Tff7b72&Tff7b72& Tb4b4b4(Tb4b4b4(Te6edf3bufTb4b4b4[T79c0ff1Tb4b4b4] Tff7b72& Te6edf3IRQ_TX_DONE_MASK_8XTb4b4b4) Tff7b72=Tff7b72= T79c0ff0Tb4b4b4)Tb4b4b4) Tb4b4b4{
Te6edf3bufTb4b4b4[T79c0ff0Tb4b4b4] Tff7b72= T79c0ff0x00Tb4b4b4;
Te6edf3bufTb4b4b4[T79c0ff1Tb4b4b4] Tff7b72= T79c0ff0x00Tb4b4b4;
Te6edf3executeOpcodeReadTb4b4b4(Te6edf3OP_GET_IRQ_STATUS_8XTb4b4b4, Te6edf3bufTb4b4b4, T79c0ff2Tb4b4b4)Tb4b4b4;
Te6edf3yieldTb4b4b4(Tb4b4b4)Tb4b4b4;
Tb4b4b4}
Tff7b72if Tb4b4b4(Tff7b72!Tb4b4b4(Te6edf3millisTb4b4b4(Tb4b4b4) Tff7b72< Te6edf3w_timeoutTb4b4b4)Tb4b4b4) Tb4b4b4{ Te6edf3timed_out Tff7b72= Tffa657trueTb4b4b4; Tb4b4b4}
T8b949e// clear IRQ's
Tffa657uint8_t Te6edf3maskTb4b4b4[T79c0ff2Tb4b4b4]Tb4b4b4;
Te6edf3maskTb4b4b4[T79c0ff0Tb4b4b4] Tff7b72= T79c0ff0x00Tb4b4b4;
Te6edf3maskTb4b4b4[T79c0ff1Tb4b4b4] Tff7b72= Te6edf3IRQ_TX_DONE_MASK_8XTb4b4b4;
Te6edf3executeOpcodeTb4b4b4(Te6edf3OP_CLEAR_IRQ_STATUS_8XTb4b4b4, Te6edf3maskTb4b4b4, T79c0ff2Tb4b4b4)Tb4b4b4;
Tff7b72if Tb4b4b4(Te6edf3timed_outTb4b4b4) Tb4b4b4{ Tff7b72return T79c0ff0Tb4b4b4; Tb4b4b4}
Tff7b72else Tb4b4b4{ Tff7b72return T79c0ff1Tb4b4b4; Tb4b4b4}
Tb4b4b4}
Tffa657unsigned Tffa657long Te6edf3preamble_detected_at Tff7b72= T79c0ff0Tb4b4b4;
Tff7b72extern Tffa657long Te6edf3lora_preamble_time_msTb4b4b4;
Tff7b72extern Tffa657long Te6edf3lora_header_time_msTb4b4b4;
Tffa657bool Te6edf3false_preamble_detected Tff7b72= Tffa657falseTb4b4b4;
Tffa657bool Td2a8ffsx128x::dcdTb4b4b4(Tb4b4b4) Tb4b4b4{
Tffa657uint8_t Te6edf3bufTb4b4b4[T79c0ff2Tb4b4b4] Tff7b72= Tb4b4b4{T79c0ff0Tb4b4b4}Tb4b4b4; Te6edf3executeOpcodeReadTb4b4b4(Te6edf3OP_GET_IRQ_STATUS_8XTb4b4b4, Te6edf3bufTb4b4b4, T79c0ff2Tb4b4b4)Tb4b4b4;
Tffa657uint32_t Te6edf3now Tff7b72= Te6edf3millisTb4b4b4(Tb4b4b4)Tb4b4b4;
Tffa657bool Te6edf3header_detected Tff7b72= Tffa657falseTb4b4b4;
Tffa657bool Te6edf3carrier_detected Tff7b72= Tffa657falseTb4b4b4;
Tff7b72if Tb4b4b4(Tb4b4b4(Te6edf3bufTb4b4b4[T79c0ff1Tb4b4b4] Tff7b72& Te6edf3IRQ_HEADER_DET_MASK_8XTb4b4b4) Tff7b72!Tff7b72= T79c0ff0Tb4b4b4) Tb4b4b4{ Te6edf3header_detected Tff7b72= Tffa657trueTb4b4b4; Te6edf3carrier_detected Tff7b72= Tffa657trueTb4b4b4; Tb4b4b4}
Tff7b72else Tb4b4b4{ Te6edf3header_detected Tff7b72= Tffa657falseTb4b4b4; Tb4b4b4}
Tff7b72if Tb4b4b4(Tb4b4b4(Te6edf3bufTb4b4b4[T79c0ff0Tb4b4b4] Tff7b72& Te6edf3IRQ_PREAMBLE_DET_MASK_8XTb4b4b4) Tff7b72!Tff7b72= T79c0ff0Tb4b4b4) Tb4b4b4{
Te6edf3carrier_detected Tff7b72= Tffa657trueTb4b4b4;
Tff7b72if Tb4b4b4(Te6edf3preamble_detected_at Tff7b72=Tff7b72= T79c0ff0Tb4b4b4) Tb4b4b4{ Te6edf3preamble_detected_at Tff7b72= Te6edf3nowTb4b4b4; Tb4b4b4}
Tff7b72if Tb4b4b4(Te6edf3now Tff7b72- Te6edf3preamble_detected_at Tff7b72> Te6edf3lora_preamble_time_ms Tff7b72+ Te6edf3lora_header_time_msTb4b4b4) Tb4b4b4{
Te6edf3preamble_detected_at Tff7b72= T79c0ff0Tb4b4b4;
Tff7b72if Tb4b4b4(Tff7b72!Te6edf3header_detectedTb4b4b4) Tb4b4b4{ Te6edf3false_preamble_detected Tff7b72= Tffa657trueTb4b4b4; Tb4b4b4}
Tffa657uint8_t Te6edf3clearbufTb4b4b4[T79c0ff2Tb4b4b4] Tff7b72= Tb4b4b4{T79c0ff0Tb4b4b4}Tb4b4b4; Te6edf3clearbufTb4b4b4[T79c0ff0Tb4b4b4] Tff7b72= Te6edf3IRQ_PREAMBLE_DET_MASK_8XTb4b4b4;
Te6edf3executeOpcodeTb4b4b4(Te6edf3OP_CLEAR_IRQ_STATUS_8XTb4b4b4, Te6edf3clearbufTb4b4b4, T79c0ff2Tb4b4b4)Tb4b4b4;
Tb4b4b4}
Tb4b4b4}
T8b949e// TODO: Maybe there's a way of unlatching the RSSI
T8b949e// status without re-activating receive mode?
Tff7b72if Tb4b4b4(Te6edf3false_preamble_detectedTb4b4b4) Tb4b4b4{ Te6edf3sx128x_modemTb4b4b4.Te6edf3receiveTb4b4b4(Tb4b4b4)Tb4b4b4; Te6edf3false_preamble_detected Tff7b72= Tffa657falseTb4b4b4; Tb4b4b4}
Tff7b72return Te6edf3carrier_detectedTb4b4b4;
Tb4b4b4}
Tffa657uint8_t Td2a8ffsx128x::currentRssiRawTb4b4b4(Tb4b4b4) Tb4b4b4{
Tffa657uint8_t Te6edf3byte Tff7b72= T79c0ff0Tb4b4b4;
Te6edf3executeOpcodeReadTb4b4b4(Te6edf3OP_CURRENT_RSSI_8XTb4b4b4, Tff7b72&Te6edf3byteTb4b4b4, T79c0ff1Tb4b4b4)Tb4b4b4;
Tff7b72return Te6edf3byteTb4b4b4;
Tb4b4b4}
Tffa657int Te6edf3ISR_VECT Td2a8ffsx128x::currentRssiTb4b4b4(Tb4b4b4) Tb4b4b4{
Tffa657uint8_t Te6edf3byte Tff7b72= T79c0ff0Tb4b4b4;
Te6edf3executeOpcodeReadTb4b4b4(Te6edf3OP_CURRENT_RSSI_8XTb4b4b4, Tff7b72&Te6edf3byteTb4b4b4, T79c0ff1Tb4b4b4)Tb4b4b4;
Tffa657int Te6edf3rssi Tff7b72= Tff7b72-Te6edf3byte Tff7b72/ T79c0ff2Tb4b4b4;
Tff7b72return Te6edf3rssiTb4b4b4;
Tb4b4b4}
Tffa657uint8_t Td2a8ffsx128x::packetRssiRawTb4b4b4(Tb4b4b4) Tb4b4b4{
Tffa657uint8_t Te6edf3bufTb4b4b4[T79c0ff5Tb4b4b4] Tff7b72= Tb4b4b4{T79c0ff0Tb4b4b4}Tb4b4b4;
Te6edf3executeOpcodeReadTb4b4b4(Te6edf3OP_PACKET_STATUS_8XTb4b4b4, Te6edf3bufTb4b4b4, T79c0ff5Tb4b4b4)Tb4b4b4;
Tff7b72return Te6edf3bufTb4b4b4[T79c0ff0Tb4b4b4]Tb4b4b4;
Tb4b4b4}
Tffa657int Te6edf3ISR_VECT Td2a8ffsx128x::packetRssiTb4b4b4(Tffa657uint8_t Te6edf3pkt_snr_rawTb4b4b4) Tb4b4b4{
T8b949e// TODO: May need more calculations here
Tffa657uint8_t Te6edf3bufTb4b4b4[T79c0ff5Tb4b4b4] Tff7b72= Tb4b4b4{T79c0ff0Tb4b4b4}Tb4b4b4;
Te6edf3executeOpcodeReadTb4b4b4(Te6edf3OP_PACKET_STATUS_8XTb4b4b4, Te6edf3bufTb4b4b4, T79c0ff5Tb4b4b4)Tb4b4b4;
Tffa657int Te6edf3pkt_rssi Tff7b72= Tff7b72-Te6edf3bufTb4b4b4[T79c0ff0Tb4b4b4] Tff7b72/ T79c0ff2Tb4b4b4;
Tff7b72return Te6edf3pkt_rssiTb4b4b4;
Tb4b4b4}
Tffa657uint8_t Te6edf3ISR_VECT Te6edf3sx128xTff7b72:Tff7b72:Te6edf3packetSnrRawTb4b4b4(Tb4b4b4) Tb4b4b4{
Tffa657uint8_t Te6edf3bufTb4b4b4[T79c0ff5Tb4b4b4] Tff7b72= Tb4b4b4{T79c0ff0Tb4b4b4}Tb4b4b4;
Te6edf3executeOpcodeReadTb4b4b4(Te6edf3OP_PACKET_STATUS_8XTb4b4b4, Te6edf3bufTb4b4b4, T79c0ff5Tb4b4b4)Tb4b4b4;
Tff7b72return Te6edf3bufTb4b4b4[T79c0ff1Tb4b4b4]Tb4b4b4;
Tb4b4b4}
Tffa657float Te6edf3ISR_VECT Te6edf3sx128xTff7b72:Tff7b72:Te6edf3packetSnrTb4b4b4(Tb4b4b4) Tb4b4b4{
Tffa657uint8_t Te6edf3bufTb4b4b4[T79c0ff5Tb4b4b4] Tff7b72= Tb4b4b4{T79c0ff0Tb4b4b4}Tb4b4b4;
Te6edf3executeOpcodeReadTb4b4b4(Te6edf3OP_PACKET_STATUS_8XTb4b4b4, Te6edf3bufTb4b4b4, T79c0ff5Tb4b4b4)Tb4b4b4;
Tff7b72return Tffa657floatTb4b4b4(Te6edf3bufTb4b4b4[T79c0ff1Tb4b4b4]Tb4b4b4) Tff7b72* T79c0ff0.25Tb4b4b4;
Tb4b4b4}
Tffa657long Te6edf3sx128xTff7b72:Tff7b72:Te6edf3packetFrequencyErrorTb4b4b4(Tb4b4b4) Tb4b4b4{
T8b949e// TODO: Implement this, page 120 of sx1280 datasheet
Tffa657int32_t Te6edf3freqError Tff7b72= T79c0ff0Tb4b4b4;
Tff7b72const Tffa657float Te6edf3fError Tff7b72= T79c0ff0.0Tb4b4b4;
Tff7b72return Tff7b72static_castTff7b72<Tffa657longTff7b72>Tb4b4b4(Te6edf3fErrorTb4b4b4)Tb4b4b4;
Tb4b4b4}
Tffa657void Te6edf3sx128xTff7b72:Tff7b72:Te6edf3flushTb4b4b4(Tb4b4b4) Tb4b4b4{ Tb4b4b4}
Tffa657int Te6edf3ISR_VECT Te6edf3sx128xTff7b72:Tff7b72:Te6edf3availableTb4b4b4(Tb4b4b4) Tb4b4b4{ Tff7b72return Te6edf3_rxPacketLength Tff7b72- Te6edf3_packetIndexTb4b4b4; Tb4b4b4}
Tffa657size_t Te6edf3sx128xTff7b72:Tff7b72:Te6edf3writeTb4b4b4(Tffa657uint8_t Te6edf3byteTb4b4b4) Tb4b4b4{ Tff7b72return Te6edf3writeTb4b4b4(Tff7b72&Te6edf3byteTb4b4b4, Tff7b72sizeofTb4b4b4(Te6edf3byteTb4b4b4)Tb4b4b4)Tb4b4b4; Tb4b4b4}
Tffa657size_t Te6edf3sx128xTff7b72:Tff7b72:Te6edf3writeTb4b4b4(Tff7b72const Tffa657uint8_t Tff7b72*Te6edf3bufferTb4b4b4, Tffa657size_t Te6edf3sizeTb4b4b4) Tb4b4b4{
Tff7b72if Tb4b4b4(Tb4b4b4(Te6edf3_payloadLength Tff7b72+ Te6edf3sizeTb4b4b4) Tff7b72> Te6edf3MAX_PKT_LENGTHTb4b4b4) Tb4b4b4{ Te6edf3size Tff7b72= Te6edf3MAX_PKT_LENGTH Tff7b72- Te6edf3_payloadLengthTb4b4b4; Tb4b4b4}
Te6edf3writeBufferTb4b4b4(Te6edf3bufferTb4b4b4, Te6edf3sizeTb4b4b4)Tb4b4b4;
Te6edf3_payloadLength Tff7b72= Te6edf3_payloadLength Tff7b72+ Te6edf3sizeTb4b4b4;
Tff7b72return Te6edf3sizeTb4b4b4;
Tb4b4b4}
Tffa657int Te6edf3ISR_VECT Te6edf3sx128xTff7b72:Tff7b72:Te6edf3readTb4b4b4(Tb4b4b4) Tb4b4b4{
Tff7b72if Tb4b4b4(Tff7b72!Te6edf3availableTb4b4b4(Tb4b4b4)Tb4b4b4) Tb4b4b4{ Tff7b72return T79c0ff-1Tb4b4b4; Tb4b4b4}
T8b949e// If received new packet
Tff7b72if Tb4b4b4(Te6edf3_packetIndex Tff7b72=Tff7b72= T79c0ff0Tb4b4b4) Tb4b4b4{
Tffa657uint8_t Te6edf3rxbufTb4b4b4[T79c0ff2Tb4b4b4] Tff7b72= Tb4b4b4{T79c0ff0Tb4b4b4}Tb4b4b4;
Te6edf3executeOpcodeReadTb4b4b4(Te6edf3OP_RX_BUFFER_STATUS_8XTb4b4b4, Te6edf3rxbufTb4b4b4, T79c0ff2Tb4b4b4)Tb4b4b4;
Tffa657int Te6edf3sizeTb4b4b4;
T8b949e// If implicit header mode is enabled, read packet length as payload length instead.
T8b949e// See SX1280 datasheet v3.2, page 92
Tff7b72if Tb4b4b4(Te6edf3_implicitHeaderMode Tff7b72=Tff7b72= T79c0ff0x80Tb4b4b4) Tb4b4b4{
Te6edf3size Tff7b72= Te6edf3_payloadLengthTb4b4b4;
Tb4b4b4} Tff7b72else Tb4b4b4{
Te6edf3size Tff7b72= Te6edf3rxbufTb4b4b4[T79c0ff0Tb4b4b4]Tb4b4b4;
Tb4b4b4}
Te6edf3_fifo_rx_addr_ptr Tff7b72= Te6edf3rxbufTb4b4b4[T79c0ff1Tb4b4b4]Tb4b4b4;
Tff7b72if Tb4b4b4(Te6edf3size Tff7b72> T79c0ff255Tb4b4b4) Tb4b4b4{ Te6edf3size Tff7b72= T79c0ff255Tb4b4b4; Tb4b4b4}
Te6edf3readBufferTb4b4b4(Te6edf3_packetTb4b4b4, Te6edf3sizeTb4b4b4)Tb4b4b4;
Tb4b4b4}
Tffa657uint8_t Te6edf3byte Tff7b72= Te6edf3_packetTb4b4b4[Te6edf3_packetIndexTb4b4b4]Tb4b4b4;
Te6edf3_packetIndexTff7b72+Tff7b72+Tb4b4b4;
Tff7b72return Te6edf3byteTb4b4b4;
Tb4b4b4}
Tffa657int Te6edf3sx128xTff7b72:Tff7b72:Te6edf3peekTb4b4b4(Tb4b4b4) Tb4b4b4{
Tff7b72if Tb4b4b4(Tff7b72!Te6edf3availableTb4b4b4(Tb4b4b4)Tb4b4b4) Tb4b4b4{ Tff7b72return T79c0ff-1Tb4b4b4; Tb4b4b4}
Tffa657uint8_t Te6edf3b Tff7b72= Te6edf3_packetTb4b4b4[Te6edf3_packetIndexTb4b4b4]Tb4b4b4;
Tff7b72return Te6edf3bTb4b4b4;
Tb4b4b4}
Tffa657void Te6edf3sx128xTff7b72:Tff7b72:Te6edf3onReceiveTb4b4b4(Tffa657voidTb4b4b4(Tff7b72*Te6edf3callbackTb4b4b4)Tb4b4b4(Tffa657intTb4b4b4)Tb4b4b4) Tb4b4b4{
Te6edf3_receive_callback Tff7b72= Te6edf3callbackTb4b4b4;
Tff7b72if Tb4b4b4(Te6edf3callbackTb4b4b4) Tb4b4b4{
Te6edf3pinModeTb4b4b4(Te6edf3_dio0Tb4b4b4, Te6edf3INPUTTb4b4b4)Tb4b4b4;
T8b949e// Set preamble and header detection irqs, plus dio0 mask
Tffa657uint8_t Te6edf3bufTb4b4b4[T79c0ff8Tb4b4b4]Tb4b4b4;
T8b949e// Set irq masks, enable all
Te6edf3bufTb4b4b4[T79c0ff0Tb4b4b4] Tff7b72= T79c0ff0xFFTb4b4b4;
Te6edf3bufTb4b4b4[T79c0ff1Tb4b4b4] Tff7b72= T79c0ff0xFFTb4b4b4;
T8b949e// On the SX1280, no RxDone IRQ is generated if a packet is received with
T8b949e// an invalid header, but the modem will be taken out of single RX mode.
T8b949e// This can cause the modem to not receive packets until it is reset
T8b949e// again. This is documented as Errata 16.2 in the SX1280 datasheet v3.2
T8b949e// (page 150) Below, the header error IRQ is mapped to dio0 so that the
T8b949e// modem can be set into RX mode again on reception of a corrupted
T8b949e// header.
T8b949e// set dio0 masks
Te6edf3bufTb4b4b4[T79c0ff2Tb4b4b4] Tff7b72= T79c0ff0x00Tb4b4b4;
Te6edf3bufTb4b4b4[T79c0ff3Tb4b4b4] Tff7b72= Te6edf3IRQ_RX_DONE_MASK_8X Tff7b72| Te6edf3IRQ_HEADER_ERROR_MASK_8XTb4b4b4;
T8b949e// Set dio1 masks
Te6edf3bufTb4b4b4[T79c0ff4Tb4b4b4] Tff7b72= T79c0ff0x00Tb4b4b4;
Te6edf3bufTb4b4b4[T79c0ff5Tb4b4b4] Tff7b72= T79c0ff0x00Tb4b4b4;
T8b949e// Set dio2 masks
Te6edf3bufTb4b4b4[T79c0ff6Tb4b4b4] Tff7b72= T79c0ff0x00Tb4b4b4;
Te6edf3bufTb4b4b4[T79c0ff7Tb4b4b4] Tff7b72= T79c0ff0x00Tb4b4b4;
Te6edf3executeOpcodeTb4b4b4(Te6edf3OP_SET_IRQ_FLAGS_8XTb4b4b4, Te6edf3bufTb4b4b4, T79c0ff8Tb4b4b4)Tb4b4b4;
Tff7b72#Tff7b72ifdef SPI_HAS_NOTUSINGINTERRUPT
Te6edf3SPITb4b4b4.Te6edf3usingInterruptTb4b4b4(Te6edf3digitalPinToInterruptTb4b4b4(Te6edf3_dio0Tb4b4b4)Tb4b4b4)Tb4b4b4;
Tff7b72#Tff7b72endif
Te6edf3attachInterruptTb4b4b4(Te6edf3digitalPinToInterruptTb4b4b4(Te6edf3_dio0Tb4b4b4)Tb4b4b4, Te6edf3onDio0RiseTb4b4b4, Te6edf3RISINGTb4b4b4)Tb4b4b4;
Tb4b4b4} Tff7b72else Tb4b4b4{
Te6edf3detachInterruptTb4b4b4(Te6edf3digitalPinToInterruptTb4b4b4(Te6edf3_dio0Tb4b4b4)Tb4b4b4)Tb4b4b4;
Tff7b72#Tff7b72ifdef SPI_HAS_NOTUSINGINTERRUPT
Te6edf3_spiModemTff7b72-Tff7b72>Te6edf3notUsingInterruptTb4b4b4(Te6edf3digitalPinToInterruptTb4b4b4(Te6edf3_dio0Tb4b4b4)Tb4b4b4)Tb4b4b4;
Tff7b72#Tff7b72endif
Tb4b4b4}
Tb4b4b4}
Tffa657void Te6edf3sx128xTff7b72:Tff7b72:Te6edf3receiveTb4b4b4(Tffa657int Te6edf3sizeTb4b4b4) Tb4b4b4{
Tff7b72if Tb4b4b4(Te6edf3size Tff7b72> T79c0ff0Tb4b4b4) Tb4b4b4{
Te6edf3implicitHeaderModeTb4b4b4(Tb4b4b4)Tb4b4b4;
T8b949e// Tell radio payload length
T8b949e//_rxPacketLength = size;
T8b949e//_payloadLength = size;
T8b949e//setPacketParams(_preambleLength, _implicitHeaderMode, _payloadLength, _crcMode);
Tb4b4b4} Tff7b72else Tb4b4b4{
Te6edf3explicitHeaderModeTb4b4b4(Tb4b4b4)Tb4b4b4;
Tb4b4b4}
Te6edf3rxAntEnableTb4b4b4(Tb4b4b4)Tb4b4b4;
T8b949e// On the SX1280, there is a bug which can cause the busy line
T8b949e// to remain high if a high amount of packets are received when
T8b949e// in continuous RX mode. This is documented as Errata 16.1 in
T8b949e// the SX1280 datasheet v3.2 (page 149)
T8b949e// Therefore, the modem is set to single RX mode below instead.
T8b949e// uint8_t mode[3] = {0x03, 0xFF, 0xFF}; // Countinuous RX mode
Tffa657uint8_t Te6edf3modeTb4b4b4[T79c0ff3Tb4b4b4] Tff7b72= Tb4b4b4{T79c0ff0Tb4b4b4}Tb4b4b4; T8b949e// single RX mode
Te6edf3executeOpcodeTb4b4b4(Te6edf3OP_RX_8XTb4b4b4, Te6edf3modeTb4b4b4, T79c0ff3Tb4b4b4)Tb4b4b4;
Tb4b4b4}
Tffa657void Te6edf3sx128xTff7b72:Tff7b72:Te6edf3standbyTb4b4b4(Tb4b4b4) Tb4b4b4{
Tffa657uint8_t Te6edf3byte Tff7b72= T79c0ff0x01Tb4b4b4; T8b949e// Always use STDBY_XOSC
Te6edf3executeOpcodeTb4b4b4(Te6edf3OP_STANDBY_8XTb4b4b4, Tff7b72&Te6edf3byteTb4b4b4, T79c0ff1Tb4b4b4)Tb4b4b4;
Tb4b4b4}
Tffa657void Te6edf3sx128xTff7b72:Tff7b72:Te6edf3setPinsTb4b4b4(Tffa657int Te6edf3ssTb4b4b4, Tffa657int Te6edf3resetTb4b4b4, Tffa657int Te6edf3dio0Tb4b4b4, Tffa657int Te6edf3busyTb4b4b4, Tffa657int Te6edf3rxenTb4b4b4, Tffa657int Te6edf3txenTb4b4b4) Tb4b4b4{
Te6edf3_ss Tff7b72= Te6edf3ssTb4b4b4;
Te6edf3_reset Tff7b72= Te6edf3resetTb4b4b4;
Te6edf3_dio0 Tff7b72= Te6edf3dio0Tb4b4b4;
Te6edf3_busy Tff7b72= Te6edf3busyTb4b4b4;
Te6edf3_rxen Tff7b72= Te6edf3rxenTb4b4b4;
Te6edf3_txen Tff7b72= Te6edf3txenTb4b4b4;
Tb4b4b4}
Tffa657void Te6edf3sx128xTff7b72:Tff7b72:Te6edf3setTxPowerTb4b4b4(Tffa657int Te6edf3levelTb4b4b4, Tffa657int Te6edf3outputPinTb4b4b4) Tb4b4b4{
Tffa657uint8_t Te6edf3tx_bufTb4b4b4[T79c0ff2Tb4b4b4]Tb4b4b4;
T8b949e// RAK4631 with WisBlock SX1280 module (LIBSYS002)
Tff7b72#Tff7b72if BOARD_VARIANT == MODEL_13 || BOARD_VARIANT == MODEL_21
Tff7b72if Tb4b4b4(Te6edf3level Tff7b72> T79c0ff27Tb4b4b4) Tb4b4b4{ Te6edf3level Tff7b72= T79c0ff27Tb4b4b4; Tb4b4b4}
Tff7b72else Tff7b72if Tb4b4b4(Te6edf3level Tff7b72< T79c0ff0Tb4b4b4) Tb4b4b4{ Te6edf3level Tff7b72= T79c0ff0Tb4b4b4; Tb4b4b4}
Te6edf3_txp Tff7b72= Te6edf3levelTb4b4b4;
Tffa657int Te6edf3reg_valueTb4b4b4;
Tff7b72switch Tb4b4b4(Te6edf3levelTb4b4b4) Tb4b4b4{
Tff7b72case T79c0ff0Tb4b4b4:
Te6edf3reg_value Tff7b72= T79c0ff-18Tb4b4b4;
Tff7b72breakTb4b4b4;
Tff7b72case T79c0ff1Tb4b4b4:
Te6edf3reg_value Tff7b72= T79c0ff-16Tb4b4b4;
Tff7b72breakTb4b4b4;
Tff7b72case T79c0ff2Tb4b4b4:
Te6edf3reg_value Tff7b72= T79c0ff-15Tb4b4b4;
Tff7b72breakTb4b4b4;
Tff7b72case T79c0ff3Tb4b4b4:
Te6edf3reg_value Tff7b72= T79c0ff-14Tb4b4b4;
Tff7b72breakTb4b4b4;
Tff7b72case T79c0ff4Tb4b4b4:
Te6edf3reg_value Tff7b72= T79c0ff-13Tb4b4b4;
Tff7b72breakTb4b4b4;
Tff7b72case T79c0ff5Tb4b4b4:
Te6edf3reg_value Tff7b72= T79c0ff-12Tb4b4b4;
Tff7b72breakTb4b4b4;
Tff7b72case T79c0ff6Tb4b4b4:
Te6edf3reg_value Tff7b72= T79c0ff-11Tb4b4b4;
Tff7b72breakTb4b4b4;
Tff7b72case T79c0ff7Tb4b4b4:
Te6edf3reg_value Tff7b72= T79c0ff-9Tb4b4b4;
Tff7b72breakTb4b4b4;
Tff7b72case T79c0ff8Tb4b4b4:
Te6edf3reg_value Tff7b72= T79c0ff-8Tb4b4b4;
Tff7b72breakTb4b4b4;
Tff7b72case T79c0ff9Tb4b4b4:
Te6edf3reg_value Tff7b72= T79c0ff-7Tb4b4b4;
Tff7b72breakTb4b4b4;
Tff7b72case T79c0ff10Tb4b4b4:
Te6edf3reg_value Tff7b72= T79c0ff-6Tb4b4b4;
Tff7b72breakTb4b4b4;
Tff7b72case T79c0ff11Tb4b4b4:
Te6edf3reg_value Tff7b72= T79c0ff-5Tb4b4b4;
Tff7b72breakTb4b4b4;
Tff7b72case T79c0ff12Tb4b4b4:
Te6edf3reg_value Tff7b72= T79c0ff-4Tb4b4b4;
Tff7b72breakTb4b4b4;
Tff7b72case T79c0ff13Tb4b4b4:
Te6edf3reg_value Tff7b72= T79c0ff-3Tb4b4b4;
Tff7b72breakTb4b4b4;
Tff7b72case T79c0ff14Tb4b4b4:
Te6edf3reg_value Tff7b72= T79c0ff-2Tb4b4b4;
Tff7b72breakTb4b4b4;
Tff7b72case T79c0ff15Tb4b4b4:
Te6edf3reg_value Tff7b72= T79c0ff-1Tb4b4b4;
Tff7b72breakTb4b4b4;
Tff7b72case T79c0ff16Tb4b4b4:
Te6edf3reg_value Tff7b72= T79c0ff0Tb4b4b4;
Tff7b72breakTb4b4b4;
Tff7b72case T79c0ff17Tb4b4b4:
Te6edf3reg_value Tff7b72= T79c0ff1Tb4b4b4;
Tff7b72breakTb4b4b4;
Tff7b72case T79c0ff18Tb4b4b4:
Te6edf3reg_value Tff7b72= T79c0ff2Tb4b4b4;
Tff7b72breakTb4b4b4;
Tff7b72case T79c0ff19Tb4b4b4:
Te6edf3reg_value Tff7b72= T79c0ff3Tb4b4b4;
Tff7b72breakTb4b4b4;
Tff7b72case T79c0ff20Tb4b4b4:
Te6edf3reg_value Tff7b72= T79c0ff4Tb4b4b4;
Tff7b72breakTb4b4b4;
Tff7b72case T79c0ff21Tb4b4b4:
Te6edf3reg_value Tff7b72= T79c0ff5Tb4b4b4;
Tff7b72breakTb4b4b4;
Tff7b72case T79c0ff22Tb4b4b4:
Te6edf3reg_value Tff7b72= T79c0ff6Tb4b4b4;
Tff7b72breakTb4b4b4;
Tff7b72case T79c0ff23Tb4b4b4:
Te6edf3reg_value Tff7b72= T79c0ff7Tb4b4b4;
Tff7b72breakTb4b4b4;
Tff7b72case T79c0ff24Tb4b4b4:
Te6edf3reg_value Tff7b72= T79c0ff8Tb4b4b4;
Tff7b72breakTb4b4b4;
Tff7b72case T79c0ff25Tb4b4b4:
Te6edf3reg_value Tff7b72= T79c0ff9Tb4b4b4;
Tff7b72breakTb4b4b4;
Tff7b72case T79c0ff26Tb4b4b4:
Te6edf3reg_value Tff7b72= T79c0ff12Tb4b4b4;
Tff7b72breakTb4b4b4;
Tff7b72case T79c0ff27Tb4b4b4:
Te6edf3reg_value Tff7b72= T79c0ff13Tb4b4b4;
Tff7b72breakTb4b4b4;
Tff7b72defaultTff7b72:
Te6edf3reg_value Tff7b72= T79c0ff0Tb4b4b4;
Tff7b72breakTb4b4b4;
Tb4b4b4}
Te6edf3tx_bufTb4b4b4[T79c0ff0Tb4b4b4] Tff7b72= Te6edf3reg_value Tff7b72+ T79c0ff18Tb4b4b4;
Te6edf3tx_bufTb4b4b4[T79c0ff1Tb4b4b4] Tff7b72= T79c0ff0xE0Tb4b4b4; T8b949e// Ramping time, 20 microseconds
Te6edf3executeOpcodeTb4b4b4(Te6edf3OP_TX_PARAMS_8XTb4b4b4, Te6edf3tx_bufTb4b4b4, T79c0ff2Tb4b4b4)Tb4b4b4;
T8b949e// T3S3 SX1280 PA
Tff7b72#Tff7b72elif BOARD_VARIANT == MODEL_AC
Tff7b72if Tb4b4b4(Te6edf3level Tff7b72> T79c0ff20Tb4b4b4) Tb4b4b4{ Te6edf3level Tff7b72= T79c0ff20Tb4b4b4; Tb4b4b4}
Tff7b72else Tff7b72if Tb4b4b4(Te6edf3level Tff7b72< T79c0ff0Tb4b4b4) Tb4b4b4{ Te6edf3level Tff7b72= T79c0ff0Tb4b4b4; Tb4b4b4}
Te6edf3_txp Tff7b72= Te6edf3levelTb4b4b4;
Tffa657int Te6edf3reg_valueTb4b4b4;
Tff7b72switch Tb4b4b4(Te6edf3levelTb4b4b4) Tb4b4b4{
Tff7b72case T79c0ff0Tb4b4b4:
Te6edf3reg_value Tff7b72= T79c0ff-18Tb4b4b4;
Tff7b72breakTb4b4b4;
Tff7b72case T79c0ff1Tb4b4b4:
Te6edf3reg_value Tff7b72= T79c0ff-17Tb4b4b4;
Tff7b72breakTb4b4b4;
Tff7b72case T79c0ff2Tb4b4b4:
Te6edf3reg_value Tff7b72= T79c0ff-16Tb4b4b4;
Tff7b72breakTb4b4b4;
Tff7b72case T79c0ff3Tb4b4b4:
Te6edf3reg_value Tff7b72= T79c0ff-15Tb4b4b4;
Tff7b72breakTb4b4b4;
Tff7b72case T79c0ff4Tb4b4b4:
Te6edf3reg_value Tff7b72= T79c0ff-14Tb4b4b4;
Tff7b72breakTb4b4b4;
Tff7b72case T79c0ff5Tb4b4b4:
Te6edf3reg_value Tff7b72= T79c0ff-13Tb4b4b4;
Tff7b72breakTb4b4b4;
Tff7b72case T79c0ff6Tb4b4b4:
Te6edf3reg_value Tff7b72= T79c0ff-12Tb4b4b4;
Tff7b72breakTb4b4b4;
Tff7b72case T79c0ff7Tb4b4b4:
Te6edf3reg_value Tff7b72= T79c0ff-10Tb4b4b4;
Tff7b72breakTb4b4b4;
Tff7b72case T79c0ff8Tb4b4b4:
Te6edf3reg_value Tff7b72= T79c0ff-9Tb4b4b4;
Tff7b72breakTb4b4b4;
Tff7b72case T79c0ff9Tb4b4b4:
Te6edf3reg_value Tff7b72= T79c0ff-8Tb4b4b4;
Tff7b72breakTb4b4b4;
Tff7b72case T79c0ff10Tb4b4b4:
Te6edf3reg_value Tff7b72= T79c0ff-7Tb4b4b4;
Tff7b72breakTb4b4b4;
Tff7b72case T79c0ff11Tb4b4b4:
Te6edf3reg_value Tff7b72= T79c0ff-6Tb4b4b4;
Tff7b72breakTb4b4b4;
Tff7b72case T79c0ff12Tb4b4b4:
Te6edf3reg_value Tff7b72= T79c0ff-5Tb4b4b4;
Tff7b72breakTb4b4b4;
Tff7b72case T79c0ff13Tb4b4b4:
Te6edf3reg_value Tff7b72= T79c0ff-4Tb4b4b4;
Tff7b72breakTb4b4b4;
Tff7b72case T79c0ff14Tb4b4b4:
Te6edf3reg_value Tff7b72= T79c0ff-3Tb4b4b4;
Tff7b72breakTb4b4b4;
Tff7b72case T79c0ff15Tb4b4b4:
Te6edf3reg_value Tff7b72= T79c0ff-2Tb4b4b4;
Tff7b72breakTb4b4b4;
Tff7b72case T79c0ff16Tb4b4b4:
Te6edf3reg_value Tff7b72= T79c0ff-1Tb4b4b4;
Tff7b72breakTb4b4b4;
Tff7b72case T79c0ff17Tb4b4b4:
Te6edf3reg_value Tff7b72= T79c0ff0Tb4b4b4;
Tff7b72breakTb4b4b4;
Tff7b72case T79c0ff18Tb4b4b4:
Te6edf3reg_value Tff7b72= T79c0ff1Tb4b4b4;
Tff7b72breakTb4b4b4;
Tff7b72case T79c0ff19Tb4b4b4:
Te6edf3reg_value Tff7b72= T79c0ff2Tb4b4b4;
Tff7b72breakTb4b4b4;
Tff7b72case T79c0ff20Tb4b4b4:
Te6edf3reg_value Tff7b72= T79c0ff3Tb4b4b4;
Tff7b72breakTb4b4b4;
Tff7b72defaultTff7b72:
Te6edf3reg_value Tff7b72= T79c0ff0Tb4b4b4;
Tff7b72breakTb4b4b4;
Tb4b4b4}
Te6edf3tx_bufTb4b4b4[T79c0ff0Tb4b4b4] Tff7b72= Te6edf3reg_valueTb4b4b4;
Te6edf3tx_bufTb4b4b4[T79c0ff1Tb4b4b4] Tff7b72= T79c0ff0xE0Tb4b4b4; T8b949e// Ramping time, 20 microseconds
T8b949e// For SX1280 boards with no specific PA requirements
Tff7b72#Tff7b72else
Tff7b72if Tb4b4b4(Te6edf3level Tff7b72> T79c0ff13Tb4b4b4) Tb4b4b4{ Te6edf3level Tff7b72= T79c0ff13Tb4b4b4; Tb4b4b4}
Tff7b72else Tff7b72if Tb4b4b4(Te6edf3level Tff7b72< T79c0ff-18Tb4b4b4) Tb4b4b4{ Te6edf3level Tff7b72= T79c0ff-18Tb4b4b4; Tb4b4b4}
Te6edf3_txp Tff7b72= Te6edf3levelTb4b4b4;
Te6edf3tx_bufTb4b4b4[T79c0ff0Tb4b4b4] Tff7b72= Te6edf3level Tff7b72+ T79c0ff18Tb4b4b4;
Te6edf3tx_bufTb4b4b4[T79c0ff1Tb4b4b4] Tff7b72= T79c0ff0xE0Tb4b4b4; T8b949e// Ramping time, 20 microseconds
Tff7b72#Tff7b72endif
Te6edf3executeOpcodeTb4b4b4(Te6edf3OP_TX_PARAMS_8XTb4b4b4, Te6edf3tx_bufTb4b4b4, T79c0ff2Tb4b4b4)Tb4b4b4;
Tb4b4b4}
Tffa657void Te6edf3sx128xTff7b72:Tff7b72:Te6edf3setFrequencyTb4b4b4(Tffa657uint32_t Te6edf3frequencyTb4b4b4) Tb4b4b4{
Te6edf3_frequency Tff7b72= Te6edf3frequencyTb4b4b4;
Tffa657uint8_t Te6edf3bufTb4b4b4[T79c0ff3Tb4b4b4]Tb4b4b4;
Tffa657uint32_t Te6edf3freq Tff7b72= Tb4b4b4(Tffa657uint32_tTb4b4b4)Tb4b4b4(Tb4b4b4(Tffa657doubleTb4b4b4)Te6edf3frequency Tff7b72/ Tb4b4b4(Tffa657doubleTb4b4b4)Te6edf3FREQ_STEP_8XTb4b4b4)Tb4b4b4;
Te6edf3bufTb4b4b4[T79c0ff0Tb4b4b4] Tff7b72= Tb4b4b4(Tb4b4b4(Te6edf3freq Tff7b72>Tff7b72> T79c0ff16Tb4b4b4) Tff7b72& T79c0ff0xFFTb4b4b4)Tb4b4b4;
Te6edf3bufTb4b4b4[T79c0ff1Tb4b4b4] Tff7b72= Tb4b4b4(Tb4b4b4(Te6edf3freq Tff7b72>Tff7b72> T79c0ff8Tb4b4b4) Tff7b72& T79c0ff0xFFTb4b4b4)Tb4b4b4;
Te6edf3bufTb4b4b4[T79c0ff2Tb4b4b4] Tff7b72= Tb4b4b4(Te6edf3freq Tff7b72& T79c0ff0xFFTb4b4b4)Tb4b4b4;
Te6edf3executeOpcodeTb4b4b4(Te6edf3OP_RF_FREQ_8XTb4b4b4, Te6edf3bufTb4b4b4, T79c0ff3Tb4b4b4)Tb4b4b4;
Tb4b4b4}
Tffa657uint32_t Te6edf3sx128xTff7b72:Tff7b72:Te6edf3getFrequencyTb4b4b4(Tb4b4b4) Tb4b4b4{
T8b949e// We can't read the frequency on the sx1280
Tffa657uint32_t Te6edf3frequency Tff7b72= Te6edf3_frequencyTb4b4b4;
Tff7b72return Te6edf3frequencyTb4b4b4;
Tb4b4b4}
Tffa657void Te6edf3sx128xTff7b72:Tff7b72:Te6edf3setSpreadingFactorTb4b4b4(Tffa657int Te6edf3sfTb4b4b4) Tb4b4b4{
Tff7b72if Tb4b4b4(Te6edf3sf Tff7b72< T79c0ff5Tb4b4b4) Tb4b4b4{ Te6edf3sf Tff7b72= T79c0ff5Tb4b4b4; Tb4b4b4}
Tff7b72else Tff7b72if Tb4b4b4(Te6edf3sf Tff7b72> T79c0ff12Tb4b4b4) Tb4b4b4{ Te6edf3sf Tff7b72= T79c0ff12Tb4b4b4; Tb4b4b4}
Te6edf3_sf Tff7b72= Te6edf3sfTb4b4b4;
Te6edf3setModulationParamsTb4b4b4(Te6edf3sfTb4b4b4, Te6edf3_bwTb4b4b4, Te6edf3_crTb4b4b4)Tb4b4b4;
Te6edf3handleLowDataRateTb4b4b4(Tb4b4b4)Tb4b4b4;
Tb4b4b4}
Tffa657uint32_t Te6edf3sx128xTff7b72:Tff7b72:Te6edf3getSignalBandwidthTb4b4b4(Tb4b4b4) Tb4b4b4{
Tffa657int Te6edf3bw Tff7b72= Te6edf3_bwTb4b4b4;
Tff7b72switch Tb4b4b4(Te6edf3bwTb4b4b4) Tb4b4b4{
Tff7b72case T79c0ff0x34Tb4b4b4: Tff7b72return T79c0ff203.125E3Tb4b4b4;
Tff7b72case T79c0ff0x26Tb4b4b4: Tff7b72return T79c0ff406.25E3Tb4b4b4;
Tff7b72case T79c0ff0x18Tb4b4b4: Tff7b72return T79c0ff812.5E3Tb4b4b4;
Tff7b72case T79c0ff0x0ATb4b4b4: Tff7b72return T79c0ff1625E3Tb4b4b4;
Tb4b4b4}
Tff7b72return T79c0ff0Tb4b4b4;
Tb4b4b4}
Tffa657void Te6edf3sx128xTff7b72:Tff7b72:Te6edf3setSignalBandwidthTb4b4b4(Tffa657uint32_t Te6edf3sbwTb4b4b4) Tb4b4b4{
Tff7b72if Tb4b4b4(Te6edf3sbw Tff7b72<Tff7b72= T79c0ff203.125E3Tb4b4b4) Tb4b4b4{ Te6edf3_bw Tff7b72= T79c0ff0x34Tb4b4b4; Tb4b4b4}
Tff7b72else Tff7b72if Tb4b4b4(Te6edf3sbw Tff7b72<Tff7b72= T79c0ff406.25E3Tb4b4b4) Tb4b4b4{ Te6edf3_bw Tff7b72= T79c0ff0x26Tb4b4b4; Tb4b4b4}
Tff7b72else Tff7b72if Tb4b4b4(Te6edf3sbw Tff7b72<Tff7b72= T79c0ff812.5E3Tb4b4b4) Tb4b4b4{ Te6edf3_bw Tff7b72= T79c0ff0x18Tb4b4b4; Tb4b4b4}
Tff7b72else Tb4b4b4{ Te6edf3_bw Tff7b72= T79c0ff0x0ATb4b4b4; Tb4b4b4}
Te6edf3setModulationParamsTb4b4b4(Te6edf3_sfTb4b4b4, Te6edf3_bwTb4b4b4, Te6edf3_crTb4b4b4)Tb4b4b4;
Te6edf3handleLowDataRateTb4b4b4(Tb4b4b4)Tb4b4b4;
Te6edf3optimizeModemSensitivityTb4b4b4(Tb4b4b4)Tb4b4b4;
Tb4b4b4}
T8b949e// TODO: add support for new interleaving scheme, see page 117 of sx1280 datasheet
Tffa657void Te6edf3sx128xTff7b72:Tff7b72:Te6edf3setCodingRate4Tb4b4b4(Tffa657int Te6edf3denominatorTb4b4b4) Tb4b4b4{
Tff7b72if Tb4b4b4(Te6edf3denominator Tff7b72< T79c0ff5Tb4b4b4) Tb4b4b4{ Te6edf3denominator Tff7b72= T79c0ff5Tb4b4b4; Tb4b4b4}
Tff7b72else Tff7b72if Tb4b4b4(Te6edf3denominator Tff7b72> T79c0ff8Tb4b4b4) Tb4b4b4{ Te6edf3denominator Tff7b72= T79c0ff8Tb4b4b4; Tb4b4b4}
Te6edf3_cr Tff7b72= Te6edf3denominator Tff7b72- T79c0ff4Tb4b4b4;
Te6edf3setModulationParamsTb4b4b4(Te6edf3_sfTb4b4b4, Te6edf3_bwTb4b4b4, Te6edf3_crTb4b4b4)Tb4b4b4;
Tb4b4b4}
Tff7b72extern Tffa657bool Te6edf3lora_low_datarateTb4b4b4;
Tffa657void Td2a8ffsx128x::handleLowDataRateTb4b4b4(Tb4b4b4) Tb4b4b4{
Tff7b72if Tb4b4b4(Te6edf3_sf Tff7b72> T79c0ff10Tb4b4b4) Tb4b4b4{ Te6edf3lora_low_datarate Tff7b72= Tffa657trueTb4b4b4; Tb4b4b4}
Tff7b72else Tb4b4b4{ Te6edf3lora_low_datarate Tff7b72= Tffa657falseTb4b4b4; Tb4b4b4}
Tb4b4b4}
Tffa657void Td2a8ffsx128x::optimizeModemSensitivityTb4b4b4(Tb4b4b4) Tb4b4b4{ Tb4b4b4} T8b949e// TODO: Check if there's anything the sx1280 can do here
Tffa657uint8_t Td2a8ffsx128x::getCodingRate4Tb4b4b4(Tb4b4b4) Tb4b4b4{ Tff7b72return Te6edf3_cr Tff7b72+ T79c0ff4Tb4b4b4; Tb4b4b4}
Tffa657void Td2a8ffsx128x::setPreambleLengthTb4b4b4(Tffa657long Te6edf3preamble_symbolsTb4b4b4) Tb4b4b4{ Te6edf3setPacketParamsTb4b4b4(Te6edf3preamble_symbolsTb4b4b4, Te6edf3_implicitHeaderModeTb4b4b4, Te6edf3_payloadLengthTb4b4b4, Te6edf3_crcModeTb4b4b4)Tb4b4b4; Tb4b4b4}
Tffa657void Td2a8ffsx128x::setSyncWordTb4b4b4(Tffa657int Te6edf3swTb4b4b4) Tb4b4b4{ Tb4b4b4} T8b949e// TODO: Implement
Tffa657void Td2a8ffsx128x::enableTCXOTb4b4b4(Tb4b4b4) Tb4b4b4{ Tb4b4b4} T8b949e// TODO: Need to check how to implement on sx1280
Tffa657void Td2a8ffsx128x::disableTCXOTb4b4b4(Tb4b4b4) Tb4b4b4{ Tb4b4b4} T8b949e// TODO: Need to check how to implement on sx1280
Tffa657void Td2a8ffsx128x::sleepTb4b4b4(Tb4b4b4) Tb4b4b4{ Tffa657uint8_t Te6edf3byte Tff7b72= T79c0ff0x00Tb4b4b4; Te6edf3executeOpcodeTb4b4b4(Te6edf3OP_SLEEP_8XTb4b4b4, Tff7b72&Te6edf3byteTb4b4b4, T79c0ff1Tb4b4b4)Tb4b4b4; Tb4b4b4}
Tffa657uint8_t Td2a8ffsx128x::getTxPowerTb4b4b4(Tb4b4b4) Tb4b4b4{ Tff7b72return Te6edf3_txpTb4b4b4; Tb4b4b4}
Tffa657uint8_t Td2a8ffsx128x::getSpreadingFactorTb4b4b4(Tb4b4b4) Tb4b4b4{ Tff7b72return Te6edf3_sfTb4b4b4; Tb4b4b4}
Tffa657void Td2a8ffsx128x::enableCrcTb4b4b4(Tb4b4b4) Tb4b4b4{ Te6edf3_crcMode Tff7b72= T79c0ff0x20Tb4b4b4; Te6edf3setPacketParamsTb4b4b4(Te6edf3_preambleLengthTb4b4b4, Te6edf3_implicitHeaderModeTb4b4b4, Te6edf3_payloadLengthTb4b4b4, Te6edf3_crcModeTb4b4b4)Tb4b4b4; Tb4b4b4}
Tffa657void Td2a8ffsx128x::disableCrcTb4b4b4(Tb4b4b4) Tb4b4b4{ Te6edf3_crcMode Tff7b72= T79c0ff0Tb4b4b4; Te6edf3setPacketParamsTb4b4b4(Te6edf3_preambleLengthTb4b4b4, Te6edf3_implicitHeaderModeTb4b4b4, Te6edf3_payloadLengthTb4b4b4, Te6edf3_crcModeTb4b4b4)Tb4b4b4; Tb4b4b4}
Tffa657void Td2a8ffsx128x::setSPIFrequencyTb4b4b4(Tffa657uint32_t Te6edf3frequencyTb4b4b4) Tb4b4b4{ Te6edf3_spiSettings Tff7b72= Te6edf3SPISettingsTb4b4b4(Te6edf3frequencyTb4b4b4, Te6edf3MSBFIRSTTb4b4b4, Te6edf3SPI_MODE0Tb4b4b4)Tb4b4b4; Tb4b4b4}
Tffa657void Td2a8ffsx128x::explicitHeaderModeTb4b4b4(Tb4b4b4) Tb4b4b4{ Te6edf3_implicitHeaderMode Tff7b72= T79c0ff0Tb4b4b4; Te6edf3setPacketParamsTb4b4b4(Te6edf3_preambleLengthTb4b4b4, Te6edf3_implicitHeaderModeTb4b4b4, Te6edf3_payloadLengthTb4b4b4, Te6edf3_crcModeTb4b4b4)Tb4b4b4; Tb4b4b4}
Tffa657void Td2a8ffsx128x::implicitHeaderModeTb4b4b4(Tb4b4b4) Tb4b4b4{ Te6edf3_implicitHeaderMode Tff7b72= T79c0ff0x80Tb4b4b4; Te6edf3setPacketParamsTb4b4b4(Te6edf3_preambleLengthTb4b4b4, Te6edf3_implicitHeaderModeTb4b4b4, Te6edf3_payloadLengthTb4b4b4, Te6edf3_crcModeTb4b4b4)Tb4b4b4; Tb4b4b4}
Tffa657void Td2a8ffsx128x::dumpRegistersTb4b4b4(Te6edf3StreamTff7b72& Te6edf3outTb4b4b4) Tb4b4b4{ Tff7b72for Tb4b4b4(Tffa657int Te6edf3i Tff7b72= T79c0ff0Tb4b4b4; Te6edf3i Tff7b72< T79c0ff128Tb4b4b4; Te6edf3iTff7b72+Tff7b72+Tb4b4b4) Tb4b4b4{ Te6edf3outTb4b4b4.Te6edf3printTb4b4b4(Ta5d6ff"Ta5d6ff0xTa5d6ff"Tb4b4b4)Tb4b4b4; Te6edf3outTb4b4b4.Te6edf3printTb4b4b4(Te6edf3iTb4b4b4, Te6edf3HEXTb4b4b4)Tb4b4b4; Te6edf3outTb4b4b4.Te6edf3printTb4b4b4(Ta5d6ff"Ta5d6ff: 0xTa5d6ff"Tb4b4b4)Tb4b4b4; Te6edf3outTb4b4b4.Te6edf3printlnTb4b4b4(Te6edf3readRegisterTb4b4b4(Te6edf3iTb4b4b4)Tb4b4b4, Te6edf3HEXTb4b4b4)Tb4b4b4; Tb4b4b4} Tb4b4b4}
Te6edf3sx128x Te6edf3sx128x_modemTb4b4b4;
Tff7b72#Tff7b72endif
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